The present invention relates generally to integrated injection logic (I.sup.2 L) circuits and, more particularly, to a low-voltage, high-noise immunity I.sup.2 L interface which occupies a substantially reduced chip area than heretofore obtained.
I.sup.2 L logic circuits have enjoyed ever increasing usage in recent years. Circuit density on integrated circuit chips has increased dramatically through I.sup.2 L design techniques as well as permitting significant reductions in power consumption.
Frequently it is necessary to control the actuation of I.sup.2 L circuitry from the outside world. That is, suitable switching must be provided, controllable by appropriate means, such as grounding or ungrounding of a bonding pad accessible from outside the associated integrated circuit chip. When interfacing an I.sup.2 L circuit to the outside world on an integrated circuit, a large injection current, as well as the necessity of incorporating a low-pass RC network (see FIG. 1) is required for each I.sup.2 L gate whose base is connected directly to an associated chip bonding pad.
These precautions are unavoidable and are necessary to prevent any printed circuit board leakage currents and any RF signal energy, which may otherwise be coupled into the pad, from seriously degrading circuit performance. However, the incorporation of the low-pass filter results in a considerable area of the IC chip being occupied. Further, the increased injection current constitutes an undesirable drain on the IC chip itself.